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| TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 INTRODUCTION The S5C7212X01 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera. 48-QFP-0707 FEATURES * Compatible with both EIA and CCIR mode ( EIA : S5F325NW02 / S5F325NU02 CCIR : S5F329PW02 / S5F329PU02 ) Built in auto iris function (Electronic Exposure) Mirror mode timing generation Field interlace mode only Timing and sync one chip IC Oscillation frequency EIA : 19.06992MHz, CCIR : 18.93750MHz ORDERING INFORMATION Device S5C7212X01-E0R0 Package 48-QFP-0707 Operating -20 C - 75 C * * * * * APPLICATION * B/W CCD Camera BLOCK DIAGRAM XSUB XSG1 XSG3 25 H4 H3 H1 H2 XV2 XV1 XV3 38 37 36 35 33 30 29 28 27 26 24 22 SHP SHD CL 43 X2 41 X1 40 TS2 45 GATE2 1/2 GATE1 XV4 RG 21 1/606 Horizontal ROM F/F 18 17 16 15 14 13 CLP1 CLP2 CLP3 DFDO CLEN WIN TS1 46 TS0 47 PWR 48 1/525 or 1/625 High/Low Control Shutter Speed ROM Vertical ROM Shutter Speed Count F/F Shutter Speed Control 1 MD2 2 MD1 3 EE1 4 EE2 7 FLD 8 PBLK 9 CSYNC 10 CBLK 11 VD 12 HD 1 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD PIN DESCRIPTION No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol MD2 MD1 EE1 EE2 VSS1 VDD1 FLD PBLK CSYNC CBLK VD HD WIN CLEN DFDO CLP3 CLP2 CLP1 VSS2 VDD2 SHD SHP VSS3 XV4 XSG3 V3 XSG1 XV1 XV2 XSUB VDD3 VSS4 I/O I I I I O O O O O O O O O O O O O O O O O O O O O Description CCIR/EIA mode selection NORMAL/MIRROR mode selection EE mode control input 1 EE mode control input 2 Ground +5V Field separation pulse Pre - blanking pulse Composite Sync.pulse Composite Blanking pulse Vertical driving pulse Horizontal driving pulse Window pulse 1/2 HD frequency pulse 1/2 VD frequency pulse Clamp pulse 3 (Dummy black level) Clamp pulse 2 (Optical black level) Clamp pulse 1 (Optical black level) Ground +5V Data Sample & Hold pulse Pre - Charge Sample & Hold pulse Ground Vertical transfer clock 4 Read out Pulse 3 Vertical transfer clock 3 Read out Pulse 1 Vertical transfer clock 1 Vertical transfer clock 2 Shutter speed control for auto iris +5V Ground Remark * Information (1) * Information (1) * Information (2) * Information (2) 2 TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol RG VDD4 H2 H1 H3 H4 VSS5 X1 X2 VDD5 CL VSS6 TS2 TS1 TS0 PWR I/O O O O O O I O O O I I I Reset gate pulse +5V Description Remark Horizontal transfer pulse 2 ( Mirror mode) Horizontal transfer pulse 1 ( Normal mode' 1' H) Horizontal transfer pulse 3 ( Normal mode' 2' H) Horizontal transfer pulse 4 ( Mirror mode ) Ground Oscillation clock Input EIA : 19,069928MHz CCIR : 18.93750MHz Oscillation clock Output +5V 1/2 Oscillation clock EIA : 9.53496MHz Ground Test Input 2 Test Input 1 Test Input 0 Power On Reset CCIR : 9.46875MHz Information 1) MD2 and MD1 mode selection ( Pull - down ) MD2 L MD1 L H H L H EIA NORMAL EIA MIRROR CCIR NORMAL CCIR MIRROR MODE Information 2 ) EE2 and EE1 shutter speed mode selection ( Pull - up ) EE2 L EE1 L H H L H MODE SHUTTER SPEED STOP SHUTTER SPEED UP SHUTTER SPEED DOWN SHUTTER SPEED STOP 3 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD ABSOLUTE MAXIMUM RATINGS Characteristics Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol VCC VI VO TOPR TSTG Value 7 VSS-0.5 - VDD+0.5 VSS-0.5 - VDD+0.5 -20 - +75 -55 - +150 Unit V V V C C ELECTRICAL CHARACTERISTICS (VDD=5V, Ta=25C, unless otherwise specified) Characteristics Supply Voltage Input Voltage 2 Symbol VDD VIH VIL Output Voltage 1 VOH1 VOL1 Output Voltage 2 (CL, RG, SHP, SHD) Output Voltage 3 (H1, H2, H3, H4) VOH2 VOL2 VOH3 VOL3 Test Condition IOH1 = -2mA IOL1 = 4mA IOH2 = -4mA IOL2 = 8mA IOH3 = -8mA IOL3 = 8mA Min 4.75 0.7VDD VDD-0.5 VDD-0.5 VDD-0.5 Typ 5.0 Max 5.25 0.3VDD 0.6 0.6 0.6 Unit V V V V V V V V V 4 TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 AC CHARACTERISTICS tr twh 90% tf 0.9VDD 10% twl 0.1VDD twh PULSES XSG1, XSG3 XV1, XV2, XV3, XV4 H1, H2, H3, H4 RG XSUB SHP, SHD, CLP1, CLP2, CLP3, DFD0, CLEN, WIN, HD, VD, CBLK, CSYNC, FLD 26 11 1.5 32 13 2.0 26 Min. 2.3 Typ. Max. Min. 2.5 twl Typ. Max. Min. tr Typ. 0.5 0.015 Max. Min. tf Typ. Max. 0.5 0.24 12 11 5 0.5 0.5 12 Unit us us ns ns us 32 51 11 5 13 14 16 13 14 16 ns 5 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD OPERATING PRINCIPLES & METHODS POWER ON RESET S5C7212X01 has two reset methods. The one is power on reset and the other is normal reset. When user wants to use power on reset, which generates an automatic reset signal that is needed to initialize the S5C7212X01 internal system when power is on, user should connect the 1000pF capacitor to the PWR ( pin 48 ) terminal. Power on reset system has an internal 100Kohm pull up resister. So, user can control reset signal timing when user changes the value of the capacitor, which is connected to the PWR terminal. When user wants to use normal reset, user should remove the capacitor from the PWR terminal, and supply the reset signal to the PWR terminal. 48 S5C7212X01 KS7212 RESET SIGNAL 48 KS7212 S5C7212X01 1000pF 2.4 ~ 2.6 V 840ns Fig. 1 POWER ON RESET Fig. 2 NORMAL RESET When using the u-Com system, the reset signal can be supplied three times, and times of 1 signal should be larger than four times of CL clock. 6 TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 APPLICATION CIRCUIT ( EIA , NORMAL MODE ) TO CCD TO VERTICAL DRIVER VDD 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 19.0699MHz X-tal 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 S5C7212X01 KS7212 TIMING & SYNC GEN TIMING & SYNCGEN. 20 19 18 17 16 15 14 13 VDD TO SIGNAL PROCESSOR * Application circuit for normal mode EIA : 19.06992MHz CCIR: 18.93750MHz 7 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD HIGH SPEED TIMING RELATIONSHIP X1 H1 PG CCD OUT SHP SHD 8 TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 CCD VERTICAL DRIVING PULSE TIMING DIAGRAM 2.0uS 1.1uS 2.5uS XSG1 39.5uS EVEN ODD XSG2 HD V1 V2 V3 V4 V1 V2 V3 V4 43.5uS 2.5uS 9 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD HORIZONTAL TIMING CHART FOR EIA 6.36 10.76 4.89 1.47 2.45 26.89 4.86 EQSYNC 10 EVEN VD ODD VD HSYNC VSYNC HD Unit : us TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 HORIZONTAL TIMING CHART FOR CCIR MODE 6.41 11.70 4.93 1.48 2.47 27.07 EQSYNC EVEN VD ODD VD HSYNC VSYNC HD Unit : us 11 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD HORIZONTAL TIMING CHART FOR MIRROR EIA MODE 1/2H 10.76 2.45 4.86 EVEN VD ODD VD HSYNC VSYNC CLP1 CLP2 12 CLP3 HD Unit : us TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 HORIZONTAL TIMING CHART FOR MIRROR CCIR MODE 6.41 11.70 2.745 4.93 EQSYNC ODD VD VSYNC CLP1 CLP2 CLP3 HD Unit : us 13 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR OSC1 14 SHD SHP PG H1 H2 H3 H4 EIA VERTICAL TIMING CHART FIELD E FIELD O HD 9H EIA VERTICAL TIMING CHART VD CSYNC 20H CBLK TIMING & SYNC. GENERATOR FOR B/W CCD FLD 80H WIN FIELD O FIELD E HD 9H VD CSYNC 20H CBLK FLD 80.5H WIN S5C7212X01 15 S5C7212X01 CCIR VERTICAL TIMING CHART 16 CCIR VERTICAL TIMING CHART FIELD O FIELD E HD 7.5H VD CSYNC 25H CBLK FLD WIN 97H FIELD O FIELD E HD 7.5H VD CSYNC 25H CBLK FLD TIMING & SYNC. GENERATOR FOR B/W CCD WIN 96.5H VERTICAL TIMING CHART FOR EIA FLD VD VERTICAL TIMING CHART FOR EIA BLK HD 10 15 20 25 260 265 270 275 280 285 290 520 5 4 3 2 1 525 TIMING & SYNC. GENERATOR FOR B/W CCD XSG1 XSG2 V1 V2 V3 V4 24 6 246 135 1 35 492 493 13 5 246 13 57 2468 CCD OUT 491 492 CLP1 CLP2 CLP3 PBLK S5C7212X01 17 S5C7212X01 VERTICAL TIMING CHART FOR CCIR 18 VERTICAL TIMING CHART FOR CCIR FLD VD BLK HD 335 10 15 20 25 310 340 315 320 325 330 620 5 4 3 2 1 625 XSG1 XSG2 V1 V2 V3 V4 246 135 2 46 13 5 135 582 583 246 582 581 13 5 7 24 68 CCD OUT CLP1 CLP2 CLP3 TIMING & SYNC. GENERATOR FOR B/W CCD PBLK S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD PACKAGE DIMENSION 48-QFP-0707 unit : mm 9.00 + 0.30 - 7.00 + 0.20 - 0~ 8 0.1 3 +0 - 0 .10 . 05 9.00 + 0.30 - 7.00 - 0.20 + 0.10 MAX # 48 #1 0.18 + 0.10 - 0.50 0.10 MAX ( 0.75 ) 0.00 MIN 1.40 + 0.10 - 1.60 MAX 19 0.50 + 0.20 - |
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